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Designing Products for the Human Experience User interfaces can differentiate a product, improve its ease-of-use, increase reliability, lower cost and much more. With the complexity of today's electronic systems, designing a user-friendly input or output device can make all the difference in the world in the success of a product. FPGA-based systems are no different in their need to interact, collect user input and present user output. In this course design engineers will learn how new software-based, companion solutions featured on the Avnet Spartan-6 LX16 platform greatly simplify the addition of USB interfaces, drive low-cost segment LCDs, create touch-sensitive interfaces, and save power and cost. See how the new programmable system-on-chip approach can enhance an FPGA-based solution and offer maximum design flexibility.
Key Takeaways
- Learn how to design an elegant, reliable touch-sensing interface
- Explore ways to differentiate a product with low-cost, custom segment LCDs
- Take advantage of low-cost USB interfaces to connect a system to a host PC
- See how to save power and cost through clever design techniques employed on the new Xilinx Spartan-6 LX16 platform designed by Avnet
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Designing with the Xilinx Virtex®-6 PCIe Gen2 Endpoint Block This course introduces design engineers to the PCIe Gen2 block embedded in Virtex®-6 devices. Design engineers will learn the basic building blocks of the Virtex-6 PCIe block such as clock and reset interface, transaction layer interface, management interface, memory interface, transceiver interface, and configuration and status interface. Implementing a power supply for the PCIe PHY (GTX transceivers) and providing a low jitter high-quality clock source to the PCIe block is also discussed. In addition, this course will address system level performance analysis in order to identify the backend memory speed requirements for meeting the PCIe data transfer rate, and design engineers will learn how to design with the Virtex-6 PCIe block using the Xilinx PCIe wizard.
Key Takeaways
- Understand the key elements of the new Virtex-6 integrated PCIe Gen2 block
- Learn how to implement the proper powering and clocking techniques for the Virtex-6 GTX transceivers and PCIe block
- Identify the backend memory requirements needed to meet the PCIe data transfer rates
- See how to use the PCIe wizard GUI to ease PCIe block design
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Designing with Xilinx Spartan®-6 Gigabit Transceivers and the PCIe Endpoint Block The objective of this course is to introduce design engineers to Spartan®-6 high-speed GTP transceivers and the Spartan-6 integrated PCIe endpoint block. This course covers the basic building blocks of the Spartan-6 GTP transceivers such as encoding, decoding, channel bonding, clock correction, CRC and comma detection. Implementing various GTP transceiver analog voltages and providing a low jitter high-quality clock source to the transceivers is also discussed. The course will demonstrate how to use the ChipScope Pro Serial I/O Toolkit to perform Bit Error Ratio analysis of one or more GTPs.
This course also introduces design engineers to the PCIe endpoint block embedded in the Spartan-6 devices. Design engineers will learn the basic building blocks of the Spartan-6 PCIe endpoint block such as clock and reset interface, transaction layer interface, management interface, memory interface, transceiver interface, and configuration and status interface.
Key Takeaways
- Understand the key elements of the new Spartan-6 GTP serial transceivers
- Learn how to implement the various GTP transceiver analog voltages as well as the reference clock input to the transceiver
- Discover how to use the ChipScope Pro Serial I/O Toolkit to perform Bit Error Ratio analysis of one or more GTXs
- Review the building blocks of the Spartan-6 integrated PCIe endpoint block and see how to use the PCIe wizard GUI to speed the implementation of PCIe design
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FPGA-based Wireless Communications Systems Design Designer engineers of wireless communications systems face the challenge of delivering systems with the flexibility to support both current and next-generation communications standards. This course will present Xilinx FPGA-based digital front-end solutions for software-defined radio systems supporting existing and emerging standards such as WCDMA, CDMA2000, WiMAX and LTE. Key components include the digital up conversion (DUC), digital down conversion (DDC) with fractional rate change, crest-factor reduction (CFR) and digital pre-distortion. The I/F signal chain will extend to the analog domain using industry-leading, high-speed data converter modules on Virtex-6 development platforms. Solutions featuring Virtex-6 GTX transceivers with JESD204A serial interface data converters will be presented. Key performance metrics such as PAPR reduction, EVM and spectral-mask compliance will be verified in real-time within the MATLAB®/Simulink® from The MathWorks™ DSP modeling environment using hardware co-simulation over Gigabit Ethernet, as well as signal analysis test equipment for communications.
Key Takeaways
- Understand the latest portfolio of Xilinx wireless solutions for multi-mode, multi-standard radio card and remote radio-head equipment applications
- Explore solutions around the newest high-speed converters
- Discover how to optimize performance at the analog/digital boundary using features of the Virtex-6
- Learn about performance metrics for wireless communications standards
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Fundamentals of FPGA-based Video Design New Spartan®-6 FPGAs offer unique I/O standards and hard memory controllers that make them an ideal choice for a wide range of video applications. Xilinx also provides an enhanced collection of video and image processing IP cores that facilitate the development of video and image processing designs. During this course, design engineers will learn how to implement a picture-in-picture application using a dual image sensor input with an image processing pipeline, video scaling, video frame buffer and LCD panel controller IP. Explanation of the image sensor and LCD panel technology and interfaces will also be reviewed.
Key Takeaways
- Understand the basics of video processing interfaces, design techniques and FPGA-based implementations
- Learn how the Spartan-6 family provides a basis for highly flexible video solutions
- See the latest Xilinx video IP demonstrated in example applications
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High-speed Clocking: Challenges, Pitfalls and Solutions In today's high-speed systems, clocking design is becoming more of an issue than in the past. The Spartan-6 and Virtex-6 FPGAs contain multiple clocking capabilities and resources on-chip, which can simplify some of the design issues associated with clocking. However, achieving optimal performance in sampling systems involving high-speed data converters still requires external clock circuits with special attention to jitter and phase noise at the system-level. This course will explain the various FPGA on-chip resources available, including the Mixed-Mode Clock Managers, PLLs, DCMs, BUFH, GCLK and BUFG, when they should be used and why. Design engineers will also learn about several external clocking solutions, why they are necessary and how they support high performance sampling systems.
Key Takeaways
- Learn about the various FPGA on-chip clocking resources
- Determine the best use for built-in features such as PLLs, DCMs, GCLKs and more
- Understand the relationship between jitter, phase noise and SNR in sampled systems
- Discover methods for managing multiple clock domains
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Implementing an FPGA-based Peripheral in an Intel® Atom™-based System FPGAs have a long history of residing next to off-the-shelf processors as a way to add custom peripheral functions or accelerate performance as co-processor engines. The interfaces between the processor and FPGA have evolved over the years, with PCI Express becoming the newest interface of choice. This course explores the practical implementation of a Spartan FPGA family as a custom expansion peripheral for the new Intel® Atom™ processor. Connected via a single lane PCIe interface, design engineers will explore the how-to steps of creating the PCIe interface in the FPGA, connecting an example user peripheral, getting Windows® Embedded to see the peripheral and running a simple Windows based application to demonstrate the complete system. This showcase solution is ideal for industrial, medical, portable, and test and measurement applications that require the low power x86 architecture of the Atom, the familiarity of the Windows operating system and the flexibility of the FPGA.
Key Takeaways
- Understand the implementation of PCI Express interface in the Xilinx Spartan FPGA family
- Learn the basics of a Windows driver, why it is needed and what it does
- See how the combined Intel Atom and Xilinx Spartan co-development platform creates a highly flexible Windows Embedded platform for industrial, medical, portable, and test and measurement applications
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Interfacing DDR3 and LPDRAM with the Xilinx Spartan®-6 Hard Memory Controller Spartan®-6 includes a built-in memory controller capable of interfacing to DDR3 at 800 Mbps as well as supporting DDR2, DDR1 and mobile DDR. During this course, design engineers will learn about the specific features and resources of this controller and how to implement interfaces between it and user logic. Two specific design examples will be presented during the course: DDR3 for higher performance and Mobile DDR for lower power. And, two real-world design examples will be shown using the new Spartan-6 development platforms from Avnet Electronics Marketing; one of which demonstrates Spartan-6 operating with LPDDR on a battery-powered LX16 board, and the other which shows Spartan-6 with DDR3 in a high-performance application.
Key Takeaways
- Learn about the new Spartan-6 built-in memory controller and its features, and how to connect user logic to the hard core
- Understand how to achieve maximum performance with DDR3
- See how to implement low power Mobile DDR memory for power saving applications
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Interfacing to an Analog World Analog-based sensor systems are typically the most precise and cost-effective method for sensing the "real world." Converting pressure, motion, fluid flow, sound, temperature, electrical current and more into a data format that can be accurately and efficiently processed by an FPGA requires special care. How does a design engineer know what type of sensor best fits an application, what are the design issues around signal conditioning and noise mitigation, what type of converter topology and resolution is required, and how is all of this interfaced to an FPGA? Join this course and learn about the design considerations and trade-offs involved in adding high-precision sensors and converters to FPGA-based systems. This course will explore several example designs that showcase unique approaches and provide real-world solutions to these challenges.
Key Takeaways
- Learn how to process multiple sensor input signals
- See the critical effects that filtering and amplification can have on low level signals
- Understand the design considerations around analog resolution, sampling speeds and converter topologies
- Explore methods for interfacing and processing sensor input at the FPGA
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Powering Xilinx Virtex®-6 and Spartan®-6 Designing a power system for Virtex®-6 and Spartan®-6 devices can be a time-consuming task when considering the various design requirements and the variety of power solutions available. This course will provide design engineers with an understanding of the important power considerations for the latest generation of Xilinx FPGAs, and will address the power technologies available to develop an optimal power system. Power system performance during startup, static operation and dynamic events will be addressed, as well as topics such as in-rush current control, voltage tolerance constraints, transient performance and decoupling. In addition, design engineers will learn about the many tradeoffs in power supply design (i.e., efficiency, cost and size) and how they apply to low power and medium power applications. Example power systems will be presented to highlight the many advantages and disadvantages of linear regulators, switching regulators and modules.
Key Takeaways
- Understand the key requirements of powering the Virtex-6 and Spartan-6 FPGAs
- Learn various techniques in designing a very low power Spartan-6 based system
- See the design trade-offs involved in using linear regulators, switchers and integrated modules
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Xilinx FPGA Co-processing with DSP Processors Increasing demand for applications with high-performance, digital signal processing capabilities is leading design engineers to combine DSPs with FPGA co-processors. This approach leverages the combined benefits of high-level processor-based software design with the parallel DSP computation power of FPGAs.
This course explores design techniques using MATLAB® and Simulink® to develop real-time image processing algorithms on Avnet platforms that combine a DSP processor and a FPGA. Simulink is an environment for multi-domain simulation for dynamic and embedded systems from The MathWorks. Topics will cover system-level simulation, optimal algorithm partitioning, acceleration of hardware co-simulation over Ethernet, and automatic code generation for DSP and FPGA co-processors.
Key Takeaways
- Learn how FPGAs can enhance the performance and functionality of DSP-based video applications
- Discover example interface architectures and partitioning techniques to optimize co-processing performance
- Understand the basics of Model-Based Design and see how these advanced tools can accelerate development with improved simulation and code generation
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Xilinx Networking: 10/100/1000 to Real-Time Network connectivity in the embedded world is mainstream technology. Yet many design engineers struggle to satisfy operational and performance goals within their cost, power and real estate budgets. Most designs have unique demands that impact the construction of both hardware and software platforms. Applications such as EtherCAT or SerCOS-III require specialized IP, or IEEE 1588 components may be used for real-time network transactions
This course examines all of the available networking options, starting from the lowest hardware layers to the top of the TCP/IP protocol stack. It will uncover some advantages for including an FPGA in system design. And, it will explore the new area of real-time Ethernet to see how this is becoming another factor to consider in product development. Regardless of an application's space, designer engineers will take away knowledge, tips and tradeoffs that will help them get the most out of the next networked design.
Key Takeaways
- Discover how to use Xilinx ISE® Design Suite 11 for embedded network designs
- See how system architecture choices affect performance and cost
- Understand how a Xilinx FPGA can improve a network project
- Learn to recognize common networking problems and correct them
- Find new applications for leading edge technologies, such as Real Time Industrial Networking and IEEE 1588
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