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Aldec HDL Simulators
Aldec HDL Simulators Active-HDL™ and Riviera-PRO™ offer a complete verification
environment including design creation, common kernel simulation, VHDL, Verilog®,
SystemVerilog, SystemC, Assertions language support, advanced debugging and coverage
tools. Aldec Simulators include the most Advanced Verification Technologies, such
as Assertion-based Verification (ABV), Electronic System Level (ESL), Transaction
Level Modeling (TLM), Open Verification Methodology (OVM) and Design Rule Checking
(DRC). Aldec simulators support Xilinx® FPGAs and multi-FPGA devices and applications.
Product Information: www.hdlsimulator.com
XFest Special Offer!
$1,995 Mixed Language Simulator
Active-HDL ™ Designer Edition provides FPGA designers with industry proven IEEE mixed-language
simulation support for VHDL, Verilog® and SystemVerilog (Design), with 2X-plus performance
gains over FPGA vendor supplied RTL simulators, encrypted IP support and no limitations
on FPGA device size all. Active-HDL Designer Edition is available today as a node
locked, one year time-based, Windows® License for $1,995 USD/1,396.50
Euro/198,000 Yen or a floating one year time-based, Windows License
for $2,495 USD/1746.50 Euro/247,500 Yen.
Product Information: http://www.aldec.com/DesignerEdition
DSP Functional Verification & Co-Simulation Solution
Pain-Free DSP Functional Verification can be achieved. Use Aldec’Äôs seamless high-performance
verification platform, which interfaces HDL simulation with the rich mathematical
computing environment provided by The Mathworks MATLAB® and Simulink® products and
Xilinx® System Generator™. Engineers can save development time, by improving algorithm
analysis, debug, verification and implementation using Aldec’Äôs seamless solution.
View Recorded Webcast
Aldec Design Rule Checker
ALINT™ is a VHDL, Verilog and Mixed Language Design Rule Checking Tool used to analyze
HDL source code against a comprehensive set of FPGA and ASIC design guidelines for
early bug detection. ALINT reduces risk when developing complex multi-million gate
FPGAs and ASICs by resolving structural, coding and consistency problems early in
the design cycle. ALINT includes cross-probing between the source code and error
messages, advanced rule configuration and in-depth analysis capabilities. Product
Information: http://www.aldec.com/products/alint
Evaluate
http://www.aldec.com/downloads
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