JEDEC JESD204A – The New New Thing in Data Converters

• In 2008, JEDEC released a revision to the 2006 JESD204 data converter interface specification called JEDEC JESD204A

• The "A" version of the specification addresses key shortcomings of the original standard

  • Support for multiple data converters on multiple 3.125 Gbps data lanes

    • The multiple lane support means that there is no arbitrary limit to the data converter sample rate bandwidth (previously, the bandwidth was limited to 312.5 MB/sec) because multiple data lanes can be assigned to each DAC and ADC channel in JESD204A

  • Embedded protocol support for the precise sample time-alignment of multiple data lanes

    • JESD204A data converters support phase-coherent quadrature sampling, which is fundamental for the OFDM-based signal processing at the foundation of wireless communications standards including LTE and WiMAX

  
  

• JEDEC JESD204A allows data converter manufacturers to significantly reduce the number of interconnect wires to the logic device with which they communicate

  • A dual-channel 14-bit ADC with a JESD204A interface has 80% fewer interconnect wires than a dual-channel 14-bit ADC with a conventional low-voltage CMOS parallel interface

  • Device pin count reduction enables customer BOM cost savings

    • Plastic molding compound, bond wires, and lead frames have costs related to commodity prices, and are not subject to the economics of Moore's Law, packaging costs are becoming a higher and higher percentage of overall IC cost structures

    • JESD204A substitutes high-speed serial transceivers implemented in silicon, subject to Moore's Law, for lower bandwidth parallel I/O pins

    • Even over a short time horizon, this is a winning strategy for data converter vendors and customers, as the inexorable march of silicon economics plays out

• The fully expressed vision of JESD204A data acquisition systems includes guaranteed interoperability with FPGAs that possess the required SERDES -based transceivers

  • Provided design engineers follow the straightforward terminated transmission line PCB design rules outlined in the specification, they can expect smooth interworking of JESD204A-compliant data converters and FPGAs, bringing a new level of ease-of-use to high-speed data acquisition system design

• Once the threshold "cost of entry" has been paid in terms of adding embedded state-machine based transceivers to data converters, the sky is the limit in terms of potential embedded "smarts"

  • JESD204A includes optional data scrambling to de-correlate any data stream periodicity related to the analog signal being sampled or reconstructed

  • The standard also supports single-bit error detection, a feature well beyond the scope of conventional interfaces

  • Collectively, these features have virtually no recurring marginal cost when implemented in a modern deep submicron process technology

  • It’s possible to imagine proprietary features added to the baseline JEDEC standard for simple digital filtering (such as high pass dc blocking), peak detection and limiting, and other simple DSP functions

• The combined merits of time-aligned high-speed serial signaling, seamless FPGA interop, and intelligent bit handling are compelling enough to assure a permanent place for JEDEC JESD204A in the high-speed data converter universe